A drive circuit of a FRAM (Ferroelectric Random Access Memory) includes an address buffer circuit that buffers an applied external address signal and generates an internal address signal, and detects a transition of the internal address signal and generates address transition detection signals for respective internal address signals. The FRAM includes a composite pulse signal generating circuit which limits a subsequent generation of a composite pulse signal for a delay interval provided after a generation of a previous composite pulse signal, in generating the second composite pulse signal obtained by totaling the respective address transition detection signals. The FRAM includes an internal chip enable buffer circuit which generates an internal chip enable signal to generate an internal control signal, in response to the composite pulse signal.