A first stage circuit for a high-speed, high-resolution pipeline analog-to-digital converter (ADC) implements operational amplifier (opamp) sharing and capacitor sharing to combine the sample-and-hold (SAH) and the MDAC (multiplying digital to analog converter) functions in the first residue stage of the pipeline ADC. In one embodiment, the first stage circuit includes a sampling capacitor, an amplifier, a feedback capacitor array and a comparator. The sampling capacitor and the feedback capacitor array are configured by switches to operate in a sampling/MDAC mode, a discharge mode and a hold mode. In this manner, the sample-and-hold operation and the MDAC operation are merged into the first stage circuit of the pipeline ADC to achieve low power and high speed of operation.

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> Continuous time delta sigma ADC with dithering

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