One embodiment of the present invention provides a system that avoids
register read-after-write (RAW) hazards upon returning from a
speculative-execution mode. This system operates within a processor with
an in-order architecture, wherein the processor includes a short-latency
scoreboard that delays issuance of instructions that depend upon
uncompleted short-latency instructions. During operation, the system
issues instructions for execution in program order during execution of a
program in a normal-execution mode. Upon encountering a condition (a
launch condition) during an instruction (a launch-point instruction),
which causes the processor to enter the speculative-execution mode, the
system generates a checkpoint that can subsequently be used to return
execution of the program to the launch-point instruction, and commences
execution in the speculative-execution mode. Upon encountering a
condition that causes the processor to leave the speculative-execution
mode and return to the launch-point instruction, the system uses the
checkpoint to resume execution in the normal-execution mode from the
launch-point instruction. In doing so, the system ensures that entries
that were in the short-latency scoreboard prior to entering the
speculative-execution mode, and which are not yet resolved, are accounted
for in order to prevent register RAW hazard when resuming execution from
the launch-point instruction.