A flash memory test system capable of test time reduction and an
electrical test method using the same: The invention provides a parallel
tester that includes a first memory and a second memory. The first and
second memories are used to each supply different data to identical
addresses within a plurality of DUTs, thereby making it possible to
conduct in parallel tests such as trim tests, repair tests, and invalid
block masking test. Thus parallel testing is done to replace testing that
was previously done serially.