A frequency extension circuit, consistent with certain embodiments of the present invention has a first delay line (108) having a plurality of taps. The delay line receives a reference clock at an input with a clock rate of F.sub.REF. A second delay line (104, 150) also receives the reference clock at an input. A logic circuit (130, 134, . . . , 138, 140) combines signals from the delay line taps of the first delay line (108) with signals from the delay line taps of the second and/or first delay line (104, 150, 108) to produce a collection of clock pulses having a combined clock rate of F.sub.REF*2N. At least one of the delay lines can be locked to the reference clock using a delay locked loop. The clock pulses can be logically combined with a seed register (204) contents to produce a recursive sequence or with data for convolutional encoding, or with pilot data for correlation in a CDMA transceiver.

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> Latching mechanism and method of operation thereof

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