An interface for accessing a bank of registers is described. A controller
is coupled to receive address information, read information and write
information. The device control register interface includes: a data bus
for receiving data, pointer information and operation delineation
information; a decoder coupled to receive the read information, the write
information, the pointer information and the operation delineation
information, where the decoder is configured to provide activation
signaling responsive to information received; and the bank of registers
coupled to the decoder to receive the activation signaling and coupled to
the data bus for receiving the data, where the address information is for
the bank or registers and where a single address is used for accessing
all registers in the bank of registers.