A device and method for detecting a delay time of a circuit is provided. A test signal is fed into the circuit, the test signal including a signal edge, the occurrence of which is related to a reference time. The output signal of the circuit is sampled at predetermined times to obtain a sequence of sample values, with a first state being associated with a sample value when the output signal has a first signal value and a second state being associated with a sample value when the output signal has a second signal value. A counter counts the sample values of the sequence, to which an equal state is associated, to obtain counted sample values. A delay time is calculated using the counted number of sample values.

 
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> Method for performing timing closure on VLSI chips in a distributed environment

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