A memory cell with a charge trapping structure has multiple bias arrangements. Multiple cycles of applying the bias arrangements lowering and raising a threshold voltage of the memory cell leave a distribution of charge in the charge trapping layer. The charge interferes with the threshold voltage achievable in the memory cell. This distribution of charge is balanced by applying a charge balancing bias arrangement. The memory cell has a high work function gate, which causes the equilibrium state of the charge balancing bias arrangement to result in a lower threshold voltage.