A PLL circuit and method provides an adjustable operating frequency range by using at least two VCOs. In an embodiment of the present invention, circuit components of a PLL are adjusted in order to obtain a selected frequency range. In particular, a gain of a charge pump and resistance of a filter is adjusted responsive to a control signal. In alternate embodiments of the present invention, a voltage regulator, including an operational amplifier, is coupled to the output of the filter and the respective inputs of two VCOs. An output multiplexer then selects a VCO output responsive to the control signal. In another embodiment of the present invention, a multiplexer is coupled to the output of the voltage regulator to select which VCO receives a buffered voltage. In another embodiment of the present invention, respective operational amplifiers that may be enabled or disabled responsive to the control signal are coupled to a filter output and respective VCO inputs in order to provide an adjustable frequency range.

 
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> Memory device having serially connected resistance nodes

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