Disclosed is a computer processor (300) comprising a plurality of processing units (FU_n) and communication means (302) by which the plurality of processing units are interconnected. The communication means is dynamically configurable based on a computer program to be processed such that the processing units can selectively be arranged in at least first and second distinct configurations. The first distinct configuration (eg. FIG. 5) has a larger number of the processing units arranged in parallel than the second distinct configuration (eg. FIG. 6), and the second distinct configuration has a deeper pipeline depth than the first distinct configuration.

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