A method is disclosed for preventing circuit failures due to gate oxide leakage, and is used to efficiently check many nets of a circuit on a chip or within a macro to find logical fails due to gate oxide leakage using DC calculations, wherein the gate leakage is treated as a noise source for a static noise analysis of the circuit.

 
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> Method and system for defect evaluation using quiescent power plane current (IDDQ) voltage linearity

> Method and apparatus for manufacturing test generation

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