A circuit for reducing inrush current generated during startup of a switching power supply, which includes a reference voltage generator, an error amplifier, an oscillator, a sawtooth wave generator, a PWM comparator, an overshoot comparator, an AND gate, a R-S flip-flop, a power MOS switch, and a rectifying and filtering circuit. A division voltage outputted from the rectifying and filtering circuit is fed to the error amplifier.