A control circuit corrects duty-cycle distortion of clock signals accurately and with a fast and continuous response over a wide dynamic range. In one embodiment, the duty-cycle correction circuit includes a self-biased loop that corrects duty-cycle distortions to preferably less than +/-1%. The duty-cycle correction circuit also compensates for changes in a supply voltage. These corrections may take place on a continuous basis, not only during a testing period but also during normal operation of the host system driven by the clock signals.