A PSRAM features a mode register set (MRS) for setting a mode register at
a combined synchronous and asynchronous mode. The PSRAM having a combined
synchronous and asynchronous mode register set includes a MRS, a mode
register control unit, a plurality of control signal buffers, an address
buffer, a clock buffer, and a synchronous and asynchronous detecting
unit. Here, the plurality of control signal buffers, the address buffer
and the clock buffers are controlled by a chip selecting signal at an
asynchronous mode, and are operated synchronously with respect to an
internal clock outputted from the clock buffer regardless of the chip
selecting signal at a synchronous mode.