A simple, approximate power optimization in connection with automatic large scale circuit design using a cell library is provided. The cell library of the present invention provides active region information for each cell, and preferably also provides conventional parameters such as cell physical area and cell performance information. Typically, several cells having differing parameters correspond to each cell function provided by the library. A cost function is defined which depends on active region information, and can also depend on physical area and performance. A cell design including cells selected from the library is optimized by substitution of functionally equivalent cells from the library to minimize the cost function. Minimization of active region area provides a simple way to approximately minimize power consumption. Optionally, a second optimization can be performed with a higher fidelity power model using the approximately power-minimized design as a starting point.

 
Web www.patentalert.com

< System and method for providing adjustable read margins in a semiconductor memory

< Device, system, server, client, and method for supporting component layout design on circuit board, and program for implementing the device

> Method of analyzing semiconductor LSI circuit electrostatic discharge

> Device and method for floorplanning semiconductor integrated circuit

~ 00289