A Very Long Instruction Word (VLIW) processor having a plurality of
functional units includes a multi-ported register file that is divided
into a plurality of separate register file segments, each of the register
file segments being associated to one of the plurality of functional
units. The register file segments are partitioned into local registers
and global registers. The global registers are read and written by all
functional units. The local registers are read and written only by a
functional unit associated with a particular register file segment. The
local registers and global registers are addressed using register
addresses in an address space that is separately defined for a register
file segment/functional unit pair. The global registers are addressed
within a selected global register range using the same register addresses
for the plurality of register file segment/functional unit pairs. The
local registers in a register file segment are addressed using register
addresses in a local register range outside the global register range
that are assigned within a single register file segment/functional unit
pair. Register addresses in the local register range are the same for the
plurality of register file segment/functional unit pairs and address
registers locally within a register file segment/functional unit pair.