A microprocessor apparatus for exclusive prefetch of a block of data from memory. The apparatus includes translation logic and execution logic. The translation logic translates an extended block prefetch instruction into a micro instruction sequence directing a microprocessor to prefetch a specified number of cache lines, where the extended block prefetch instruction is encoded to direct the microprocessor to prefetch the specified number of cache lines in the exclusive state. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that requests the specified number of cache lines in the exclusive state, where the specified number of cache lines includes data entities that are to be subsequently modified, and where prefetching the specified numbers of cache lines in the exclusive state occurs parallel with execution of program instructions prior to execution of subsequent store instructions that direct the microprocessor to modify the data entities.

 
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