A data recovery circuit has a phase-locked loop for generating a plurality of clock signals; an oversampling unit for non-integer times oversampling serial data, and outputting the oversampled result as sample data formed of a plurality of bits; a pattern detector for receiving the sample data, and generating a pattern signal; a state accumulator for receiving the pattern signal, accumulating the frequency of occurrence of the pattern signal, and outputting the pattern signal having the highest frequency of occurrence as a state signal; a state selector for receiving the state signal, and generating a state selection signal for selecting bits at predetermined positions in the sample data; and a data selector for receiving the sample data, selecting bits of the sample data in response to the state selection signal, and outputting the selected bits as recovered data formed of a plurality of bits.

 
Web www.patentalert.com

< Bus clock controlling apparatus and method

< Method for recording address information on optical recording medium, optical recording medium including address information recorded thereon by the same method, and method for detecting address information recorded on the same optical recording medium

> Front panel driving apparatus

> Video-on-demand system and video viewing assisting method

~ 00273