A circuit generally comprising a plurality of read input registers, a read output register, a write input register and a plurality of write output registers is generally disclosed. The read input registers may be configured to buffer a first read signal received within a plurality of first transfers. The read output register may be configured to transmit the first read signal in a second transfer. The write input register may be configured to buffer a first write signal received in a third transfer. The write output registers may be configured to transmit the first write signal within a plurality of fourth transfers.