Circuit elements are formed in a semiconductor chip (1) and an electrode pad (11) for connection with outside is formed on the periphery of a surface of the semiconductor chip (1). On the other hand, a wiring (21) is formed on one surface of an insulating substrate (2) and an external connecting terminal (22) is formed on the other surface thereof, being connected to the wiring (21). The electrode pad (11) of the semiconductor chip (1) and the wiring (21) are bonded by an Au--Sn alloy layer (3) at the connection section thereof. As a result, there is obtained a semiconductor device of a CSP type with a structure capable of connecting the semiconductor chip and the insulating substrate to each other without applying a large pressure and a high temperature thereto, and forming a circuit element even below the electrode pad and in the vicinity thereof to enable high integration.