A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.

 
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< System supporting multiple memory modes including a burst extended data out mode

< Virtual mode virtual memory manager method and apparatus

> Method and apparatus to maintain consistency between an object store and a plurality of caches utilizing transactional updates to data caches

> Storage configurator for determining an optimal storage configuration for an application
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