A processor system and method that reduces the number of register value copying
made from alias registers to corresponding real (architectural) registers. One
method entails not performing an alias register to real register copying if the
incoming instruction does not designate a real register. Another method entails
delaying alias register to real register copying until the corresponding reorder
buffer (ROB) entry is actually written to. Yet another method entails not performing
an alias register to real register copying if the ROB entry is the same as the
existing ROB entry. And, still another method entails further delaying or stalling
the allocation of an ROB entry.