Chip area corresponding to unnecessary I/O cell sites is recovered and made usable for additional core cells and power connections by grouping I/O cells into I/O kernels of contiguous I/O cells having power connections independent of other I/O kernels and depopulating I/O cell sites in accordance with areas corresponding to I/O kernels. Since I/O kernels have dedicated power connections, no power busses are present in the depopulated I/O cell sites which can then be freely use for additional core cells, power connections or the like. This technique also allows selection of a chip of minimum required area to be determined prior to design of chip layout.

 
Web www.patentalert.com

< Establishing a secure connection with a private corporate network over a public network

< Method, system, and computer program product for type-based table navigation

> Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization

> Mechanism for converting text output into objects

~ 00248