A data processing system having no system memory is disclosed. The data processing
system includes multiple processing units. The processing units have volatile cache
memories operating in a virtual address space that is greater than a real address
space. The processing units and the respective volatile memories are coupled to
a storage controller operating in a physical address space that is equal to the
virtual address space. The processing units and the storage controller are coupled
to a hard disk via an interconnect. The storage controller allows the mapping of
a virtual address from one of the volatile cache memories to a physical disk address
directed to a storage location within the hard disk without transitioning through
a real address.