A data processing apparatus includes a processor core having a bank of registers.
The bank of registers include a set of registers that are used for the storage
of stack operands. Instructions from a second instruction set specifying stack
operands are translated by an instruction translator into instructions of a first
instruction set (or control signals corresponding to those instructions) specifying
register operands. These translated instructions are then executed by the processor
core. The instruction translator has multiple mapping states for controlling which
registers corresponding to which stack operands within the stack. Changes between
mapping states are carried out in dependence of stack operands being added to or
removed from the set of registers.