An integrated circuit design method and an integrated circuit design apparatus,
for increasing an efficiency of parallel processing of LSI design layout data while
retaining a hierarchical structure by use of a computer capable of processing the
data in parallel, take a first construction of making an internal cell composed
of divided cells obtained by dividing a design cell specified by design cell data
among pieces of integrated circuit design layout data on the basis of a cell division
judging criterion, and of non-divided design cells other than the divided cells,
then creating a plurality of unit groups of which data quantities are substantially
equal to each other by combining the internal cells, and executing hierarchical
parallel processing of the data contained in the internal cell per unit group,
and take a second construction of restoring a non-overlapped array data region
left by excluding a data region having overlapped data from an array data region
containing array data among pieces of integrated circuit design layout data, with
a combination of a plurality of or a single piece of array cell or unit cell.