CMOS logic LSI comprises, as a part thereof, n-channel MISFET's (Qn), p-channel
MISFET's (Qp) and a first-layer wiring (11) to a third-layer (13)
formed on a main surface of a silicon substrate (1), and as another part,
a fourth-layer wiring (14) to a seventh-layer wiring (17) formed
on a main surface of a glass substrate (30) different from the silicon substrate
(1). The main surface of the silicon substrate (1) and the main surface
of the glass substrate (30) are arranged in face-to-face relation with each
other, and a plurality of microbumps (20A) formed at the uppermost portion
of the silicon substrate (1) and a plurality of microbumps (20B)
formed at the uppermost portion of the glass substrate (30) are electrically
connected, thereby constituting the CMOS logic LSI as a whole.