An embedded controller includes a central processing unit, a memory interface for interface with an external memory, and a function block or peripheral device with a register for storing operation state information. The peripheral device includes a detection circuit, a storage unit, for example in the form of a FIFO, a multiplexer, and a direct memory access (DMA) controller. The state detection circuit activates a flag signal whenever the operation state information of the register is varied, and the FIFO stores the operation state information from the register in response to the flag signal. The multiplexer is controlled by the DMA controller and transmits the operation state information of the FIFO to an internal bus. As a result, the operation state information of the FIFO is stored in the external memory through the memory interface.