A shift register is provided to monitor the difference between the read and write
pulses to an elasticity buffer. The shift register essentially eliminates the need
for any math functions in the elasticity buffer management logic. The shift register
is as wide as the elasticity buffer is deep. In other words, for every word in
the elasticity buffer, the shift register has a corresponding bit. Each time a
word is written into the elasticity buffer without a simultaneous corresponding
read, a value of "1" is shifted from a first end into the shift register, indicating
that a space has been taken in the elasticity buffer. For every word read out of
the elasticity buffer without a simultaneous corresponding write, a value of "0"
(zero) is shifted from a second end of the shift register, indicating that one
more space is available. The elasticity buffer management logic need only monitor
the shift register value to determine whether the elasticity buffer is nearly empty
or nearly full, and if fill words need to be inserted or deleted.