A memory device may be implemented to respond to and one or more command encodings that specify different burst lengths than the burst length indicated by the current burst length setting for the memory device. For example, a memory device may include a memory array and a mode register configured to store a value indicating a current burst length. The memory array may be configured to perform a first burst access having a first burst length in response to receiving a first command encoding and to perform a second burst access having a second burst length, which does not equal the current burst length, in response to receiving a second command encoding. A memory controller may be implemented to generate to and one or more command encodings that specify different burst lengths than the burst length indicated by the current burst length setting for a targeted memory device.