An A/D-conversion circuit is provided that includes: a counter, which outputs a count value CT; a voltage generation circuit, which generates a monotonically increasing or monotonically decreasing analog voltage AV1; a comparator, which compares the analog voltage AV1 with an analog voltage AV2 to which A/D conversion is conducted, and outputs an signal CQ according to the comparison result; a digital filter circuit, which conducts digital filtering processing to the signal CQ and outputs a signal DQ; and a count value hold circuit EFF, which holds the count value CT from the counter based on the signal DQ. The digital filter includes hold circuits FF1 to FF3 and changes the voltage level of the signal DQ, when a pattern of the output signals Q1 to Q3 thereof matches a predetermined pattern.