A configuration of vector units, digital circuitry and associated instructions is disclosed for the parallel processing of multiple Viterbi decoder butterflies on a programmable digital signal processor (DSP) that is based on single-instruction-multiple-data (SIMD) principles and provides indirect access to vector elements. The disclosed configuration uses a processor with two vector units and associated registers, where the vector units are connected back to back for processing Viterbi decoder state metrics. Viterbi add instructions increment vectors of state metrics from a first register, performing a desired permutation of state metrics while reading them indirectly through vector pointers, and writing intermediate result vectors to a second register. Viterbi select instructions perform element-wise maximum or minimum operations on vectors from the second register to determine survivor metrics, performing a desired inverse permutation of survivor metrics while writing them back to the first register and recording the corresponding decisions in a shift register for use in a subsequent traceback operation.