Systems and methods for pre-artwork timing verification of an integrated circuit design are provided. A representative system includes a computer and a memory element associated with the computer, the memory element configured to store information related to a contemplated integrated circuit design and model functional blocks of the integrated circuit responsive to the expected signal timing behavior of signals that traverse a functional block of interest. A representative method includes the following steps: acquiring circuit information that represents a plurality of functional blocks and a plurality of conductors of a contemplated integrated circuit, where the functional blocks are modeled by a plurality of signal characteristics; receiving timing constraints used in designing each respective functional block; generating a representation of each functional block; and applying the representation in a static timing analyzer.