Memory modules and methods having a buffer clock that operates at different clock frequencies according to the operating mode

Memory modules and methods of testing memory modules are provided that include at least one memory device responsive to a memory clock signal having a memory clock frequency and a data buffer. The data buffer is responsive to a buffer clock signal having a first buffer clock frequency that is different from the memory clock frequency during a normal mode of operation and having a second buffer clock frequency that is equal to the memory clock frequency during a test mode of operation.

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