A method of evaluating a core based SoC detects and localizes faults in the cores or interconnects between the cores with high accuracy and observability. The method includes the steps of building two or more metal layers to create core I/O pads having all I/O pads and power pads on a surface of the top metal layer of the pad frame of each core, testing the SoC as a whole by applying test vectors to the SoC through chip I/O pads and evaluating response outputs of the SoC, testing each core in the SoC by applying core specific test vectors to the core through the core I/O pads on the top metal layer of the core and evaluating response outputs of the core, and finding a location of a fault when the fault is detected when testing the SoC chip as a whole or when testing each of the cores.