A virtual memory system including a local-to-global virtual address
translator for translating local virtual addresses having associated task
specific address spaces into global virtual addresses corresponding to an
address space associated with multiple tasks, and a global
virtual-to-physical address translator for translating global virtual
addresses to physical addresses. Local-to-global virtual translation is
performed by either mapping local virtual addresses to a single global
virtual address space or to multiple global virtual address spaces. The
local-to-global virtual translator includes a cell which corresponds to
each local address space for performing the translations. In a memory
system in which both data and instruction address accesses are performed,
separate cache and tag structures are employed for handling each of the
data and instruction memory accesses. In addition, the cache is
configurable such that it can be configured into a buffer portion or a
cache portion for faster cache accesses. Protection information is
provided by each of the local virtual-to-global virtual address
translator, the global virtual-to-physical address translator, the cache
tag storage, or a protection information buffer depending on whether a
cache hit, cache miss, or buffer access occurs during a given data or
instruction access. In addition, the cache is configurable such that it
can be configured into a buffer portion or a cache portion for faster
cache accesses. Memory area privilege protection is also achieved by
employing a gateway instruction which generate an address to access a
gateway storage area. The gateway storage area holds pointers to both an
instruction area and a data area. The gateway instruction branches to the
instruction area and loads the pointer to the data area.