A method for designing a semiconductor integrated circuit device for connecting
between terminals of transistors formed on a silicon wafer by metal wiring. The
method includes a first step of carrying out a schematic arrangement so as to minimize
a distance of a wiring for connecting between the transistors or wiring capacitance
based on input information on transistors; a second step of producing information
on a voltage drop value based on the schematic arrangement of the transistors;
and a third step of arranging the transistors based on the information on a voltage
drop value.