A mechanism controls a multi-thread processor so that when a fist thread encounters
a latency event to a first predefined time interval temporary control is transferred
to an alternate execution thread for duration of the first predefined time interval
and then back to the original thread. The mechanism grants full control to the
alternate execution thread when a latency event for a second predefined time interval
is encountered. The first predefined time interval is termed short latency event
whereas the second time interval is termed long latency event.