Provided is a method of designing a semiconductor device in which power
supply voltages can be applied individually and clock jitter is suppressed to avoid
lowering of logic operation rate. Specifically, plural power supply lines (WL1)
electrically connected to power supply bumps (BP1, BP2) are disposed
in parallel to the lateral array of the power supply bumps (BP1, BP2),
and power supply lines (WL2) of the lower layer which are electrically connected
to the power supply lines (WL1) are disposed in parallel to each other so
as to be orthogonal to the power supply lines (WL1) when viewed from above.
Power supply voltages (V1, V2) are assigned to two power supply lines
(WL1) that are nearest neighbors across an array of the power supply bumps
(BP1), and power supply voltages (G1, G2) are assigned to
two power supply lines (WL1) that are nearest neighbors across an array
of the power supply bumps (BP2). The power supply lines (WL2) are
disposed in parallel to each other so as to be orthogonal to the power supply lines
(WL1) when viewed from above.
