A system for testing semiconductor die on multiple semiconductor wafers includes
a testing unit (82), a test fixture bank (84) operably coupled to
the testing unit (82), a plurality of test fixture racks (86-92)
operably coupled to the test fixture bank (84) and a plurality of wafer-interposer
assemblies (94-140) operably coupled to each of the test fixture racks (86-92).
Each of the wafer-interposer assemblies (94-140) includes a semiconductor
wafer having a plurality of semiconductor die and an interposer coupled to the
semiconductor wafer. The interposer has a first set of conductors for electrically
connecting the semiconductor die of the semiconductor wafer to a substrate and
a second set of conductors that electrically connect the semiconductor die of the
semiconductor wafer to the test fixture rack (86-92) via a connector, thereby
providing for addressing and testing of the semiconductor die.
