A method generates a test pattern for an integrated circuit (IC) design using
a
functional verification program. The functional verification program includes a
stimulus generator, an expected-response generator, and an interface defining ports
of the IC design. The method includes (a) converting input ports in the interface
into bi-directional in/out ports, (b) supplying stimuli to the converted in/out
ports and original in/out ports in the interface by executing the stimulus generator,
(c) sampling the stimuli supplied to the converted in/out ports and the original
in/out ports, and (d) recording the sampled stimuli. The method may further include
(e) creating bi-directional shadow ports in the interface, the shadow ports corresponding
to the in/out ports and output ports of the IC design, (f) supplying expected responses
to the shadow ports by executing the expected-response generator, (g) sampling
the expected responses from the shadow ports, and (h) recording the sampled expected response.
