Pipelined processor including a loosely coupled side pipe

   
   

A digital data processor having a main pipeline to which a side pipe is loosely coupled. In particular, the side pipe is coupled to the main pipeline at a point after which an instruction entering the side pipe cannot cause an exception. When such an instruction enters the first stage of the side pipe, a copy or "ghost" of this instruction is created. While the actual instruction flows down the side pipe, this ghost instruction is allowed to flow independently down the main pipeline as if it were a non-squashable no-op. When the ghost reaches the retirement stage of the main pipeline, it is retired in normal program order, regardless of the status of the actual instruction. However, in addition, each system resource that is still waiting for a result from the actual instruction is marked appropriately. When the actual instruction finally completes in the side pipe, the only consequence, other than those local to the side pipe itself, is that any results are forwarded to the awaiting resources. If it should happen that a resource has been reallocated to a more recent instruction while the actual instruction is still in flight, the forwarded result is discarded upon arrival; otherwise, the resource is updated using the forwarded result. As a result of employing such a pipe coupling mechanism, the number of pipe stages that must be traversed by instructions other than those requiring a side pipe resource may be reduced. One disclosed example of such a side pipe is a multiply accumulate unit suitable for use in digital signal processing applications, whereby the performance of control type instructions is greatly improved.

 
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