An automatic design system for designing wirings on circuit elements, includes
an input device configured to receive circuit information, a glitch searching unit
configured to search a glitch-occurring circuit element, a skew calculator configured
to calculate a skew of a clock signal, a circuit information analyzer configured
to define the calculated skew as a first target skew and determine whether the
glitch can be reduced by setting the first target, a first target skew setting
unit configured to set the first target, and a first latch insertion unit configured
to insert a first latch.
