A shared bypass bus structure for low-latency coherency controller access in a
coherent scalable switch. In a coherent scalable switch with multiple coherent
interconnect ports, distributed coherency control structures, and a crossbar interface
between them, a shared bypass bus permits data transfer between the coherent interconnect
ports and the coherency control structures while bypassing the crossbar interface.
Some embodiments may comprise scalable switches to support one or more sets of
processors with substantially independent snoop or cache coherency paths or arrangements.
