A flash memory cell array comprises a substrate, a string of memory cell structures
and source region/drain region. Each of memory cell structures includes a stack
gate structure including a select gate dielectric layer, a select gate and a gate
cap layer formed on the substrate; a spacer is set on the sidewall of the select
gate; a control gate connected to the stack gate structure is set on the one side
of the stack gate structure; a floating gate is set between the control gate and
the substrate; an inter-gate dielectric layer is set between the control gate and
the floating gate; and a tunneling dielectric layer is set between the floating
gate and the substrate. The source region/drain region is set in the substrate
near outer control gate and stack gate structure of the flash memory cell array.
