Timing verification of the LSI test data is performed as follows. In test
synthesis, a script text for static timing analysis (STA) is generated together
with a test circuit. The STA script text is used to perform static timing analysis.
Function verification is performed between a netlist generated through the test
synthesis and a timing-verified netlist based on the static timing analysis. The
function-verified netlist is released to a production division, and the netlist
is used to automatically generate a test pattern by an automatic test pattern generation
(ATPG) tool. A netlist comprising test vectors for automatic test equipment is
acquired from the generated ATPG pattern.
