Techniques are disclosed for estimating the signal propagation delays
within a circuit, based on a description of the circuit written in a hardware description
language (HDL), such as a register transfer language (RTL). Assignment statements
in the description which describe the performance of a logical function are modeled
using logic gates which perform the function described. A particular function may
be modeled using one or more logic gates depending on the number of inputs to the
function. The delay associated with performance of the function is estimated by
estimating the delay through the circuit used to model the function. Estimates
for multiple functions may be combined to estimate the total delay associated with
a particular signal path through a circuit.
