A multi-processor arrangement having an interprocessor communication path between
each of every possible pair of processors, in addition to I/O paths to and from
the arrangement, having signal processing functions configurably embedded in series
with the communication paths and/or the I/O paths. Each processor is provided with
a local memory which can be accessed by the local processor as well as by the other
processors via the communications paths. This allows for efficient data movement
from one processor's local memory to another processor's local memory, such as
commonly done during signal processing corner turning operations. Configurable
signal processing logic may be configured to host one or more signal processing
functions which allow data to be autonomously accessed from the processor local
memories, processed, and re-deposited in a local memory.
