A scaleable integrated data processing device, particularly a microcomputer,
comprises
a processing unit with one or more processors and a storage unit with one or more
memories. The data processing device is provided on a carrier substrate (S) and
comprises mutually adjacent substantially parallel layers (P, M, MP) stacked up
on each other, the processing unit and the storage unit being provided in one or
more such layers and the separate layers formed with a selected number of processors
and memories in selected combinations. In each layer are provided horizontal electrical
conducting structures which constitute electrical internal connections in the layer
and besides each layer comprises further electrical conducting structures which
provide electrical connections to other layers and to the exterior of the data
processing device. The integrated data processing device has a scaleable architecture,
such that it in principle can be configured with an almost unlimited processor
and memory capacity. Particularly can the data processing device implement various
forms of scaleable parallel architectures integrated with optimal interconnectivity
in three dimensions.
