An electronic system includes a reference clock that generates a reference clock
signal, at least one, phase-locked loop clock generator that synthesizes a derivative
clock signal from the reference clock signal, and at least one digital circuit
timed by the derivative clock signal. In addition, the electronic system includes
a phase-locked loop clock synthesis fault detector having a phase detector and
data storage for storing a historical indication of the phase of the derivative
clock signal synthesized from the reference clock signal. The phase detector detects
a change of phase of the derivative clock signals relative to the historical indication
of the phase and, in response to this detection, signals that a clock synthesis
fault has occurred.
